1. Field of the Invention
The present invention relates to monolithic capacitors. More specifically, the present invention relates to monolithic capacitors including ceramic layers and at least one pair of internal electrodes opposing each other with one of the ceramic layers therebetween, circuit boards, and circuit modules.
2. Description of the Related Art
In a power supply circuit, when voltage fluctuation increases in a power supply line, because of the impedances present in the power supply line and a ground, the operation of a circuit to be driven may become unstable, interference between circuits may occur by way of the power supply circuit, or oscillation may occur. Consequently, a decoupling capacitor is usually connected between the power supply line and the ground. The decoupling capacitor reduces the alternating current impedance between the power supply line and the ground, and suppresses fluctuation of the power supply voltage and interference between circuits.
Recently, in communication devices, such as mobile phones, and information-processing devices, such as personal computers, in order to process a large amount of information, the signal speed has been increasing. Accordingly, the clock frequency of semiconductor integrated circuits (hereinafter, which may be abbreviated as “ICs”) to be used has been increasing. As a result, noise with a high harmonic content is easily generated. Thus, it is necessary to provide stronger decoupling in IC power supply circuits.
In order to enhance the decoupling effect, it is effective to use a decoupling capacitor having an excellent impedance frequency characteristic. Examples of such a decoupling capacitor include monolithic ceramic capacitors. Monolithic ceramic capacitors have a low equivalent series inductance (ESL), and thus have a high noise absorption effect over a wider frequency band than electrolytic capacitors.
FIG. 16 is a cross-sectional view showing a structure of a monolithic capacitor 131 disclosed in Japanese Unexamined Patent Application Publication No. 11-204372 in which ESL can be reduced. In the monolithic capacitor 131, as shown in FIG. 16, both first external terminals 138 and second external terminals 139 are disposed on a principal surface 137 of a capacitor body 135. A first internal electrode 133 located in the capacitor body 135 is connected to a corresponding external terminal 138 by a corresponding first via-hole connecting portion 140, and a plurality of first internal electrodes 133 are connected to each other by first via-hole connecting portions 140. A second internal electrode 134 is connected to a corresponding second external terminal 139 by a corresponding second via-hole connecting portion 141, and a plurality of second internal electrodes 134 are connected to each other by second via-hole connecting portions 141. The first via-hole connecting portions 140 and the second via-hole connecting portions 141 are alternately arranged.
In the monolithic capacitor 131, currents flowing through the internal electrodes 133 and 134 flow a short distance and are directed in various directions, and currents flowing through the via-hole connecting portions 140 and 141 are directed opposite to each other. Thus, the magnetic fluxes cancel each other, and ESL is reduced.
In the monolithic ceramic capacitor used as the decoupling capacitor, in addition to reduction in ESL, it is required to control the equivalent series resistance (ESR). The reason for this is to prevent the fact that, when many capacitors are connected in parallel in the periphery of an IC, the impedance of the IC is extremely decreased in the vicinity of the resonant frequency of the IC, which may cause ringing, resulting in disturbance of the signal waveform in the IC.
A multilayer ceramic capacitor in which controlled ESR is achieved is disclosed in Japanese Unexamined Patent Application Publication No. 2004-47983. In the multilayer ceramic capacitor, terminal vias are composed of ruthenium oxide which is a resistive material, and correspond to the via-hole connecting portions 140 and 141 in the monolithic capacitor shown in FIG. 16. Thereby, the resistance (impedance) at the terminal vias is increased, which suppresses the disturbance of signal waveform due to the occurrence of ringing.
However, in the multilayer ceramic capacitor described above, since the resistance at the terminal vias becomes excessively high, there is a delay in an activation of the IC, which is a problem. When the multilayer ceramic capacitor is used as a decoupling capacitor, the multilayer ceramic capacitor not only prevents the interference of signals from other circuits but also supplies a complementary electric power to the IC because an electric power may be deficient during fluctuation of the power supply voltage. Consequently, when the resistance of the terminal vias becomes excessively high, electric power is prevented from being rapidly supplied from the multilayer ceramic capacitor to the IC, resulting in a delay in an activation of the IC. Furthermore, when the resistive component is present entirely in the terminal vias, the resistance of the terminal vias easily fluctuates under the influence of sintering shrinkage of the terminal vias, etc. Thus, it is difficult to adjust the resistance of the terminal vias, which is also a problem.